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"The ISE Design Suite 10.1 has been invaluable for our design team, providing up to 80 percent run time improvement. Faster run times provide tremendous savings in development time, thus speeding our time-to-market," said Yasuhiro Ooba, senior engineer in the Photonic Systems Group at Fujitsu, a leading provider of customer-focused information technology and communications solutions for the global marketplace.
"SmartXplorer provides a powerful addition to our FPGA design flow. Without SmartXplorer we had to log onto multiple servers and manage individual PAR jobs manually," said Honda Yang, logic designer at Xsigo Systems, Inc., the technology leader in data center I/O virtualization. "I was amazed to see the results of the different strategies. Using SmartXplorer, we achieved 20 percent faster performance."
Ultimate Productivity with PlanAhead Lite & Strategy Based Implementation
With the availability of the PlanAhead Lite tool in ISE(R) Foundation(TM) software, users have access to a subset of the powerful floorplanning and analysis capabilities of the award winning PlanAhead design and analysis tool. Included at no additional cost, PlanAhead Lite features the revolutionary PinAhead technology, an intuitive solution designed to simplify the complexities of managing the interface between the target FPGA and PCB. PinAhead technology facilitates early and intelligent pinout definition to eliminate many of the pinout related changes that typically happen downstream by performing design rule checks during interactive pin placement. Once the pin assignments have been completed, PinAhead provides the ability to export I/O port information through either comma separated value (CSV) files or via VHDL or Verilog headers.
With ISE Design Suite 10.1, Xilinx has also simplified the process of determining optimal implementation settings. Designers now have the ability to specify and set their own unique design goals, whether they are working to maximize performance, optimize device utilization, reduce dynamic power, or minimize implementation time. Designers using this area reduction strategy can realize an average of 10 percent better logic utilization.
Task Force Delivers Improved Verification
The ISE Design Suite 10.1 also benefits from the efforts of the company's joint collaboration with Mentor Graphics, one of the industry's leading EDA providers. Through the use of IEEE IP encrypted models, ISE Design Suite 10.1 offers up to 2X faster run times. The new performance optimized BRAM, DSP, and FIFO simulation models further reduce RTL simulation run times by an additional 2X.
Second Generation XPower Provides Improved Power Analysis and Optimization
Industry studies show meeting power budgets is a growing challenge for FPGA designers, especially as process geometries continue to shrink. The ISE Design Suite 10.1 provides capabilities for users to analyze power requirements early in the design and optimize dynamic power throughout the design process.
The second generation XPower power analysis tool enhances power estimation by providing an improved user interface to make it easy to analyze power by blocks, hierarchy, power rails and resources used. Information is presented in both text and HTML report formats. This is a significant advance from the static estimation web pages offered by other logic providers and a leap forward in providing accurate power dissipation information.
ISE Design Suite 10.1 provides power optimization that's both convenient and extensive. Using the integrated 'power optimization design goal' feature, users have a simple, one-step process to specify power optimization. With improvements in the map and place & route algorithms, users can reduce dynamic power in their designs by an average of 10 percent for 65nm Virtex(R)-5 devices and an average of 12 percent with Spartan(TM)-3 generation FPGAs.
Embedded & DSP Tool Integration
To help users achieve optimal embedded and DSP design results more quickly, ISE Design Suite 10.1 also introduces many ease-of-use enhancements to both the Xilinx embedded and DSP tools, including unified interoperability which allows users to easily add System Generator modules within the ISE Project Navigator. Inter-tool integration enhancements between EDK and System Generator for DSP technologies enable more sophisticated FPGA SoC design incorporating both embedded and signal processing.
Pricing and Availability
The ISE Design Suite 10.1 consists of ISE Foundation, Embedded Development Kit (EDK) with Platform Studio (XPS), System Generator for DSP, AccelDSP(TM) synthesis tool, ChipScope(TM) Pro analyzer and ChipScope Pro Serial I/O toolkit, PlanAhead design and analysis tool and ISE simulator. Users can install domain specific DSP, embedded and logic design products from either a DVD or electronic download. Using an electronic fulfillment process as the primary product delivery method provides users with access to not only the products they are entitled to, but evaluation versions of other Xilinx design tools.
All products in the ISE Design Suite 10.1 are immediately available with prices ranging from US $495 to $2495. Full-featured 60-day evaluation versions can be downloaded from the Xilinx web site at no charge. For more information on the ISE Design Suite 10.1, visit http://www.xilinx.com/ISE.
About Xilinx
Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit http://www.xilinx.com.
Xilinx, the Xilinx logo, Virtex, Spartan, and ISE are trademarks of Xilinx in the U.S. and other countries.
Editorial Contact: Tamara Snowden Xilinx North America (408) 879-6146 tamara.snowden@xilinx.com #0835p
SOURCE Xilinx, Inc.
http://www.xilinx.com
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