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The LMH4345 SerDes transceiver delivers jitter performance of 30 picoseconds (ps) output alignment jitter and 0.6 units interval (UI) minimum input jitter tolerance. The transmitter's ultra-low output jitter provides ample margin for meeting the Society of Motion Picture and Television Engineers (SMPTE) 424M jitter specifications. The company said the receiver's high input-jitter tolerance guarantees the deserializer will successfully receive, lock and deserialize incoming video streams that have accumulated noise, even with up to 70 percent of the signal's eye closed. SMPTE 424M is the SDI industry standard for transporting uncompressed 1080p signals at up to 60 frames per second over 3 Gbps serial links.
The LMH4345 delivers the raw analog performance of a discrete SerDes in a flexible multi-channel configuration, which until now has only been offered with more expensive, high-end field-programmable gate arrays (FPGAs). Designing with National's LMH4345 eliminates the need for expensive power supplies, noise isolation circuits, pristine reference clocks and the external voltage-controlled crystal oscillators (VCXOs) that are required by high-end FPGAs with integrated SerDes. Additionally, the LMH4345 includes four integrated SDI cable drivers, two SDI output drivers and two reclocked loop-through drivers that further reduce bill of materials (BOM), board area and system cost.
According to a release, the LMH4345 architecture leverages a 5-bit low-voltage differential signaling (LVDS) parallel bus to simplify FPGA interface. The transceiver's LVDS interface reduces electromagnetic interference (EMI), while the narrow parallel bus enables a single FPGA to support a greater number of high-speed video channels. The LMH4345 is commonly designed into broadcast video systems with National's SDI adaptive cable equalizer (LMH0344), multi-format sync separator (LMH1981) and video clock generator (LMH1982).
National's LMH4345 triple-rate SDI serializer supports 270 Mbps, 1.485 Gbps and 2.97 Gbps data rates, enabling transmission of digital video broadcasting-asynchronous serial interface (DVB-ASI), standard-definition (SMPTE 259M-C), high-definition (SMPTE 292M) and the new 3G-SDI standard (SMPTE 424M). The LMH4345's two receivers include a clock and data recovery circuit (CDR) that automatically detects the incoming serial data rate, extracts the clock and deserializes the data into a 5-bit LVDS stream to simplify interfacing with a host FPGA. Additional outputs for serial reclocked loop-through provide access to the ingested signals for real-time input monitoring. Each transmitter includes an integrated, low-bandwidth phase-lock loop (PLL) that cleans the parallel clock noise added from the FPGA, alleviating the need for external clock conditioning. The LMH4345 is housed in a small 14 mm by 14 mm, 100-pin TQFP package, the company noted in a release.
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