Synopsys Adds Incremental Signoff-Quality Design Rule Checking

Wed. October 01, 2008; Posted: 01:26 AM

Sep 30, 2008 (M2 PRESSWIRE via COMTEX) -- SNPS | Quote | Chart | News | PowerRating -- Synopsys, a provider of software and IP for semiconductor design and manufacturing, announced the addition of incremental signoff-quality Design Rule Checking (DRC) and metal fill capability to IC Compiler.

IC Compiler has accelerated hundreds of tapeouts across a broad range of technologies from 130-nm to 45-nm by providing correct-by-construction, DRC-clean layouts. As an added assurance, Synopsys is now rolling out new technology to guard against corner-case DRC violations that can remain unnoticed until the final stages of physical verification, critically impacting the tapeout schedule. The new push-button capability in IC Compiler is powered by Hercules DRC/LVS and enables place-and-route engineers to run physical verification after each block, ensuring that the final signoff verification will succeed in a single pass. Incremental capability allows users to run localized checks to verify layout modifications, reducing the turnaround time to minutes versus hours for full-chip verification.

"As we move into 65-nm and below, the number of foundry DRC checks during physical verification is growing significantly," said Keith Riley, vice president of Engineering at Intellon. "Being able to conduct DRC checking on routing layers incrementally using the foundry runset directly within IC Compiler allows us to verify quickly any possible layout modifications, such as manual Engineering Change Orders (ECOs). In early trials of the incremental capability, we have seen significant time savings in our design flow."

"By adding incremental physical verification capabilities to IC Compiler, we are enabling users to save hours by eliminating unnecessary iterations during the final stages of the tapeout," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "Running physical verification checks from within IC Compiler during the design process helps ensure that once implementation is done, final signoff will succeed in a single pass."

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For full details on Synopsys Inc (SNPS) click here. Synopsys Inc (SNPS) has Short Term PowerRatings of 5. Details on Synopsys Inc (SNPS) Short Term PowerRatings is available at This Link.

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