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According to the company, Synopsys' USB 2.0 nanoPHY mixed-signal IP, now available in a native 1.8V architecture, meets the full USB 2.0 specification including 5V short tolerance for 24 hours and 3.3V operation. This architecture helps designers embed the DesignWare USB 2.0 PHY IP into system-on-chips (SoCs) utilizing the most advanced process geometries without compromising performance or long-term reliability.
The DesignWare USB 2.0 nanoPHY IP is designed for a broad range of high-volume mobile and consumer applications where the key requirements include minimal area, minimal dynamic and leakage power consumption. In addition, the DesignWare USB 2.0 nanoPHY IP has built-in tuning circuits designed to enable quick, post-silicon adjustments to account for unexpected chip/board parasitics or process variations, without having to modify the existing design. This allows designers to increase yield and minimize the cost of expensive silicon re-spins, the company said.
The DesignWare USB 2.0 nanoPHY IP, according to the company, is part of Synopsys' complete DesignWare USB 2.0 IP solution consisting of, digital controllers, PHY and verification IP. Synopsys offers a comprehensive portfolio of USB 2.0 IP for 180-nm, 130-nm, 90-nm, 65-nm, 45-nm, and now 40-nm process technologies. The DesignWare USB 2.0 IP products have been implemented in hundreds of USB applications and are shipping in high volume production.
"Certification is important because it demonstrates that IP solutions meet USB-IF interoperability standards and are compliant to the USB 2.0 specification," said Jeff Ravencraft, USB-IF president and chairman. "The availability of Synopsys' certified USB 2.0 PHY IP in the 40-nanometer process technology enables designers to quickly introduce next-generation Hi-Speed USB products including smart phones and mobile internet devices (MIDs) to the market."
"As the leader in USB IP, Synopsys provides designers with comprehensive, high-quality USB IP solutions that are silicon-proven and certified," said John Koeter, vice president of marketing, Solutions Group at Synopsys. "Being first to achieve USB 2.0 certification with a native 1.8V architecture is an important technical milestone, enabling the continued integration of USB 2.0 PHY IP using today's 40-nanometer processes and future 32-nanometer and 28-nanometer processes."
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