Synopsys Bolsters VMM

SAN FRANCISCO, Dec 22, 2008 (ASCRIBE NEWS via COMTEX) -- SNPS | Quote | Chart | News | PowerRating -- Synopsys, a provider of software and IP for semiconductor design and manufacturing, announced the release of an expanded version of VMM, a verification methodology.

According to the company, the updated release includes new, user-driven features, such as a multi-stream scenario generator, transactor iterator and command-line options manager. Synopsys said these features increase scalability from block to system-level, ease-of-use and verification productivity. A new Performance Analyzer application further improves productivity by enabling analysis of shared design resources. The enhancements to VMM streamline the development of today's increasingly complex verification environments.

"After a thorough evaluation of competing verification methodologies, we standardized on VMM to streamline verification of our IP and microcontrollers," said Sury Maturi, director of the Design Automation Group at National Semiconductor. "The new, expanded release of VMM includes a number of enhancements that will allow us to further reduce our verification cycles, such as the multi-stream scenario generator and new test structure, which enables us to create sophisticated controllable scenarios and, consequently, achieve greater scalability and reuse of stimulus."

"As an international provider of high-end functional verification consulting services, we have deployed VMM for our clients on a range of projects across the globe," said Jason Sprott, vice president of Consulting at Verilab. "Because of our significant level of hands-on experience with verification methodologies, we were in an excellent position to help guide the evolution of VMM and contribute to the enhancements in the latest release. It now enables even higher levels of scalability, simplifies implementation and is more capable than ever at helping design teams accelerate the verification process."

"A robust and production-proven methodology is a must in order to meet today's demanding project schedules, and a strong ecosystem is equally important for ease-of-adoption," said Michael Hoyt, president and chief executive officer of Paradigm Works. "VMM not only delivers the strongest ecosystem in the industry, it also offers a suite of extremely useful applications. We have been and will continue to be part of this growing ecosystem focused on delivering applications that improve verification productivity."

Synopsys said this latest release of VMM offers a new base class that enables test writers to compile and elaborate all tests at once then select, at run-time, which test to execute. This eliminates the need for a recompile of each test, thereby speeding regression turnaround time, the company noted. In addition, a new channel recording and replay capability enables users to run entire regressions just once and perform playback later without stimulus generators for specific components of the verification environment.

"Synopsys and the EDA industry are seeing broad deployment of SystemVerilog," said Manoj Gandhi, senior vice president and general manager of the Verification Group at Synopsys. "We continue to provide technological leadership in this market with increased investments that address the growing verification challenges of our customers. The expanded release of VMM is the result of a successful and innovative collaboration between Synopsys, our customers and partners. It provides an excellent foundation for building a single, standardized verification methodology."

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